1. Field of Invention
The present invention relates to a method for circuit verification. More particularly, the present invention relates to a hardware and software co-simulation method for verifying cache access mechanism.
2. Description of Related Art
With the help of computer science, designers can use programming languages to establish software modeling for software simulation during circuit designing. By means of software simulation, designers can verify whether the function (or behavior) of circuit being designed is correct or not. Besides, designers can use hardware description language (HDL) to establish hardware modeling for hardware simulation as well, such as performing a resistor-transistor layer (RTL) simulation. Likewise, designers can verify whether the function (or behavior) of circuit being designed is correct or not by means of hardware simulation.
Mostly, designers use both hardware simulation and software simulation to verify the correctness and efficiency properties of the designed circuit. Designers can further compare the respective verification results of hardware and software co-simulation to check the reliability of the simulations.
However, the behavior verification results between the hardware simulation and the software simulation for some circuits may be different. For example, in the same non-blocking cache in pipelined CPU, the behavior verification result of software simulation differs from that of hardware simulation. That is because the software modeling is of the instruction simulation mode, during its simulation, the actual time needed by main memory to answer the requited access is neglected. FIG. 1A to FIG. 1F indicate the change of the storage state of the data memory during simulation of the hardware modeling of non-blocking cache. Here, the instructions of “LDR R1, 0×1000—0000”, “LDR R2, 0×2000—0000”, “LDR R3, 0×3000—0000” and “LDR R4, 0 ×1000—0000” are taken as the test pattern needed by the simulating operation.
FIG. 1A illustrates the initial states of way 0 data memory W0 and way 1 data memory W1 in the hardware modeling of non-blocking cache. In FIG. 1B, when CPU executes instruction “LDR R1, 0×1000—0000”, that is, data should be read from main memory address 0×1000—0000 and stored in register R1, because the data to be read does not exist in the cache, that is usually called ‘miss’, the data read from main memory at address 0×1000—0000 will first be stored into the cache of data memory W0 in order to be read by CPU.
When CPU executes instruction “LDR R2, 0×2000—0000” in succession, because the data to be read is ‘miss’, the data will be requested and read out from main memory at address 0×2000—0000, and then stored into non-used data memory W1 so as to be read by CPU, as illustrated in FIG. 1C. In sequence, when CPU executes instruction “LDR R3, 9×3000—0000”, showed in FIG. 1D, because the data to be read is ‘miss’ either, likewise, a read request is first issued to the main memory. In FIG. 1E, because the cache is the non-blocking cache, CPU will continue executing the next instruction “LDR R4, 0×1000—0000” not necessary to wait for data return, even though the cache has not obtained the data from main memory address 0×3000—0000.
In FIG. 1E, because the previous instruction is ‘miss’, the hardware modeling issues a read request to the main memory for reading and not has obtained the data yet, there is still the data of address 0×1000—0000 in the cache of data memory W0. When executing instruction “LDR R4, 0×1000—0000”, the CPU then obtains the data of address 0×1000—0000 from the cache of data memory W0, which is usually called ‘hit’. After the cache obtains the data from main memory address 0×3000—0000, as illustrated in FIG. 1F, it will select the data memory W1, which has not been accessed for longest time in data memories W0 to W1, to store the data.
FIG. 2A to FIG. 2E indicate the change of the storage state of the data memory during simulation of the software modeling of non-blocking cache. Herein, in the same way, the instructions of “LDR R1, 0×1000—0000”, “LDR R2, 0×2000—0000”, “LDR R3, 0×3000—0000” and “LDR R4, 0×1000—0000” are taken as the test samples needed by the simulation.
FIG. 2A indicates the initial states of way 0 data memory W0 and way 1 data memory W1 in the software modeling of non-blocking cache. In FIG. 2B, when CPU executes instruction “LDR R1, 0×1000—0000”, because of being ‘miss’, the data from the main memory address 0×1000—0000 is stored into the cache of data memory W0 in order to be read by the CPU. When the CPU executes instruction “LDR R2, 0×2000—0000” in succession, as shown in FIG. 2C, because the data to be read is ‘miss’, a read request for reading the main memory at address 0×2000—0000 is issued and the data of the address is read out and then stored into non-used data memory W1 so as to be read by CPU.
In sequence, when the CPU executes instruction “LDR R3, 0×3000—0000”, as showed in FIG. 2D, because of the data being ‘miss’, likewise, a request for reading is issued to the main memory. However, since it is neglected for the actual time needed by the main memory to respond the access request during the simulation of software modeling, the cache immediately obtains the data from main memory at address 0×3000—0000 and stores the data into data memory W0, which has not been accessed for the longest time in the data memory. Then, as illustrated in FIG. 2E, when the instruction “LDR R4, 0×1000—0000” is executed, because of data to be read at 0×1000—0000 being ‘miss’, likewise, the data is requested and read from the main memory at address 0×1000—0000 and stored in data memory W1, which has not been accessed for the longest time in the data memories W0 to W1. Therefore, the behavior verification results between hardware simulation and software simulation of non-blocking cache are not the same, so that the comparison between their simulation results can not be done for hardware and software co-simulation.